Pseudo Random Bit generator with VHDL

Hi Francisco,

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I'm trying to understand and test this code, yet I keep receiving errors

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Start by running the existing testbenches.

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do I have to create two separate VHDL files in QUARTUS to run this, one for the testbench and one for the LFSR?

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Quartus is for *synthesis* only. A testbench is for simulation only, and is run in Modelsim.

If you have written C-code before; you component is equivalent to your C-code, while the testbench is equivalent to a unit test.

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My goal is to generate a random set of bits in order to output a random voltage signal trough the GPIO pins in my DE2 board then I will connect it to a transmitter circuit.

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You will not get a random voltage. You will get a stream of 0s and 1s that occur in a random order.

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This circuit depends on a MOSFET, Resistor, and the transducer.

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Make sure your GPIO can drive the MOSFET correctly, eg., a power MOSFET requires more current than a GPIO can supply.

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Yet, my first step is understand how to build a LFSR to generate the signal

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Simply instantiate the LFSR component.

Here's what you need to do.

1. Start Modelsim.
2. Change directory to where ever you unzipped the zip file
    Modelsim> cd {c:\temp\lfsr_tutorial_src\prbs}
3. Source the simulation script
    Modelsim> source scripts/sim.tcl
4. Run the testbench
    Modelsim> lfsr_tb

Now read the code (VHDL and Tcl scripts), and try to understand it.

Cheers,

Dave