Pseudo Random Bit generator with VHDL

Dave, I'm trying to understand and test this code, yet I keep receiving errors do I have to create two separate VHDL files in QUARTUS to run this, one for the testbench and one for the LFSR? When does it mean that is a TESTBENCH? My goal is to generate a random set of bits in order to output a random voltage signal trough the GPIO pins in my DE2 board then I will connect it to a transmitter circuit. This circuit depends on a MOSFET, Resistor, and the transducer. Yet, my first step is understand how to build a LFSR to generate the signal

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity PRNG22 is

generic ( width : integer := 32 );

port (

clk : in std_logic;

random_num : out std_logic_vector (width-1 downto 0) --output vector

);

end PRNG22;

architecture Behavioral of PRNG22 is

begin

process(clk)

variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');

variable temp : std_logic := '0';

begin

if(rising_edge(clk)) then

temp := rand_temp(width-1) xor rand_temp(width-2);

rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);

rand_temp(0) := temp;

end if;

random_num <= rand_temp;

end process;

END Behavioral;

------------------------------------------------------

--The test bench for the code is given below:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY testbench IS

ARCHITECTURE behavior OF testbench IS

--Input and Output definitions.

signal clk : std_logic := '0';

signal random_num : std_logic_vector(3 downto 0);

-- Clock period definitions

constant clk_period : time := 1 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: entity work.random generic map (width => 4) PORT MAP (

clk => clk,

random_num => random_num

);

-- Clock process definitions

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

END