Problems using Logic Lock

To start I'm using Full Quartus 2 version 7.0 (I've been instructed by my boss not to upgrade until after the design is finished and working). I'm trying to design into a Stratix 2 EP2S60F1020I4 device.

I originally looked into and tried to start with using the Incremental Design Flow from bottom up but the design didn't seem to fit ID's requirements. So, stepping away from ID I just went with trying to Logic Lock parts of the design.

Requirements for design involving Logic Lock:

1. Preserve performance for specific high speed modules.

This I'm attempting to do by completing them and Logic Locking them in their lower

level projects and importing them into the top level.

2. Try to reduce compile times.

This is an untrue statement, what is wanted that any recompiles of the top level design

only work on those functions that have been changed and not those that haven't.

The result should be shorter compile times with design changes.

I've been trying my best to follow the Logic Locking directions given in the Quartus 2 Handbook Chapter 13: Logic Lock Design Methodology for version 7.0.

Its not working. Particularly when I import everything in I get No-fit errors where the compiler is trying to place two separate, supposedly, Logic Locked items into the exact same location. What I've been learning is that the documentation on Logic Lock is inadequate and /or in error. My last SR to Altera on this suggested I should not be back annotating. I do not see any way forward then with either Logic Lock or ID. Does any one have good information, procedures, etc. on how to use Logic Lock?

(Extremely) Detailed instructions are welcome.

Basic Design information:

The design is rather complex requiring interfacing with cameras, ADCs, DACs, Transducers, analog logic controls, very high speed transceivers and other logic.

The highest clock speed is 500MHz however this I keep to few simple functions.

I do use at least one EPLL in the design to generate three 200MHz clocks, two at 40/60

and one at 60/40 with phase shifts as required by the camera.

The transceivers, however, require an extremely low jitter clock at 125MHz which I generate from the 500MHz in logic.

All I've stated above simplifies the very unsimple design and states some of the fastest clock speeds I must deal with. It is expected that the entire design should use no more than 40% of the logic resources of this device.

There is logic running at much lower speeds and nearly all the clocks for them are generated in logic. (25MHz, 10MHz, 2MHz, 1MHZ, 100KHz, 10KHz and 2Hz)

Some of the subfunctions of the design are over 1000 LCELLs but most are not, not good for ID. The higher speed subfunctions I want to Logic Lock down their placement and routing however I do not want to lock down the slower speed functions.

EX:

The interface to the high speed transceiver(s) must run at 125MHz and requires tracking of Disparity. This needs locking down and its size is less than 300 LCELLs.

The interface to the ADCs is running at 10MHz even though its logic is making decisions based upon readings. At 10MHz this does not need to be locked down but its size is over 1100 LCELLs.