Problems using Logic Lock

Stevie,

Actually not a good plan. Because of the problems with LL and the# poor documentation on ID and LL I'm so far behind this project may be canned before I can get ID to work!

My boss read this stuff over and decided that I should upgrade so now I'm in the middle of installing v7.1+.

You asked so here's your first question:

1. I have a number of small functions that must be placed and Locked into their locations.

They occupy from less than one LAB to up to four LABs. They run at 500MHz and my experience so far has been that if I don't Lock them and their routing down the Q2 compiler at the Top Level WILL mess them up.

How do I deal with these functions in the ID methodology?

To help in understanding this here's some more info;

Two of these functions are critical and both run at 500MHz. Both generate outputs that will be Globals to ALL of the other logic. One function generates a pair of Global Reset signals shortly after FPGA configuration. The second generates two Global Clocks from the 500MHz input clock, 250MHz and 125MHz. The 500MHz is an ultra stable LVDS clock input and the 250MHz and 125MHz, particularly the 125MHz, MUST be ultra stable as well for the high speed serial transceiver devices. So PLLs are no good for these two clocks.