Problems using Logic Lock

Sounds like quite a project. OK, I'll save you the warnings about driving a clock with outputs of logic, because I'm sure you must have heard them before... Some issues are covered in http://www.alteraforum.com/forum/showthread.php?t=754. Don't assume the clock skew isn’t an issue... And try to avoid paths that cross between the clock domains as much as possible, etc etc.

To optimize your blocks with incremental compilation, you can use a bottom-up flow where they are each defined in separate Quartus II projects, or you can include them as part of a top-level project where everything is partitioned and set the rest of your design blocks with a Netlist Type of Empty while you optimize the small blocks. The top-down flow is somewhat "easier" as you have only one QII project. The two flows should be explained OK in the docs. Create Partitions, set Netlist Types, compile. I suggest you post here or file an Altera mysupport SR if you have *specific* questions that come up.

When partitioning the rest of the design, check out the guidelines in the handbook about registered boundaries, cross-partition paths etc. Also there are a few restrictions that hopefully won't aply, but I think they are all in the chapter too.

To control the blocks placement, you can assign them to small LogicLock regions before you compile or after you see the first fitter-chosen result. Use Auto-Floating regions for the first round, or set it to your desired size. If the Fitter doesn't do exactly what you want with them, you can use the Chip Planner and Resource Property Editor to move nodes around in the floorplan. This is instead of trying to back-annotate the assignments and then changing the assignments manually.

Once you have the fitting you want, whether you used LogicLock regions with Resource Property Editor or the Fitter found a good solution the first time through, set the Netlist Type to Post-fit and the Fitter preservation Level to Placement & Routing (assuming you want the routing as well) for the partition. This will tell the Fitter to re-use the database netlist next time so you get the same P&R results.

Assuming the top-down (one project) flow: Then you can set the other partitions from Empty to Source File and compile with the logic from those partitions while your small blocks are fixed in the device.

That's the basic overview. Hope it helps! Gotta go...