Problems using Logic Lock

Well... I guess I'm showing that Altera's documentation now agrees with Brad that the old LogicLock flow is not recommended any more, so you should try using incremental compilation instead. And I do think the 7.1 documentation adds a bit more, yeah.

If you are worried about conflicts, I guess the 7.0 chapter should work OK too, if you have a dog eared version of that as well! I think it had a similar example section, and the procedural stuff should all be in there. Check out the sections "Preparing a Design...", "Compiling a Design", and then the more detailed sections on "Setting the Netlist Type" and "Creating a Floorplan" (that last one is the LogicLock region bit).

Do you have specifics about the problems you had when you tried the incremental flow? I think in your posts you mostly discussed the problems with the LogicLock flow...? Maybe I (or Brad or some other users) can help address the incremental issues, so at least you are focusing your attention on the tool that Altera is promoting to meet your goals!

P.S. Your goals as stated in your first post sound just like the quoted benefits of the incremental compilation feature!

Requirements for design involving Logic Lock:

1. Preserve performance for specific high speed modules.

This I'm attempting to do by completing them and Logic Locking them in their lower

level projects and importing them into the top level.

2. Try to reduce compile times.

This is an untrue statement, what is wanted that any recompiles of the top level design

only work on those functions that have been changed and not those that haven't.

The result should be shorter compile times with design changes.