Problems using Logic Lock

Sounds like a good plan. Remember that partitions are "logical" partitions of your design hierarchy. They don't specify a location on the device floorplan.

The partition size (amount of logic per partition) is not really that important, because the tool is pretty flexible. You want to have reasonably even chunks of logic so that you'll get the compilation time savings when you change one of them. You also don't want them too small, because that will restrict cross-boundary optimization perhaps more than required to get the compilation time benefits. Just take care with the recommendations for partition boundaries, signals crossing bondaries etc. It's all in the docs.

You might be thinking about LogicLock regions, which are physical regions that you can use to isolate placement of logic to one area of the chip. Using physical regions for each partition can help ensure good quality of results when you recompile (and of course are needed to avoid placement conflicts if you want to import an already-placed partition from another team member's Quartus II project). But creating a floorplan is not always absolutely necessary. Also there are instructions in the doc that tell you how to use Auto-Floating regions to let the fitter give you a first hit at it.