Problems using Logic Lock

Stevie and Randall,

Randall first;

Did that once, God help you on a design change. Yes it can work but;

1. Your locations for that logic are frozen to those LCELL locations in the project. If you change the design or drop that part of the design from the overall project those locked LCELLs will remain there no matter what. I have a coworker who does that all the time, the only way to remove or change the logic is by scragging the project back to source and starting again. Very dangerous and extremely limiting.

Also it wasn't the logic placement that the compiler messed up but the routing. My 250MHz clock is/was a simple toggle flip-flop clocked at 500MHz. When selected to make the output a Global clock the compiler routed the toggle feedback first to the Global then back to the register. The result was a 125MHz clock due to delays. To fix it I fed the output of the toggle flip-flop to into another d-flip-flop and clocked it at 500MHz. Its output was to be the Global clock. The compiler decide I didn't need the second d-flip-flop and removed it. The result was the same 125MHz as before The fix was to set Preserve Register in the assignment editor for both flip-flops.

Stevie,

1. I don't get those skew clock or other warnings in my logic generated clock designs. I do declare the generated clocks as such in the Assignment Settings and Set them as Globals in the Assignment Editor. I follow all the steps and get them recognized as clock signals without issues.

2. I'm going to start a new thread I'll cal Designing with Incremental Design? I've read the v7.1 chapter on ID and find it a good piece of non-technical sales literature.