Problems synthesizeing infered true dual ported RAM

You have two processes that assign values to a single pin. This is like putting a vacuum cleaner in two powersockets at the same time. It is a short-circuit, and therefor not allowed. As for the clock domains, I don't know.

Thanks for your reply PietervanderStar! You're right, combining the logic to one process solves that problem, thanks. I was probably so sucked up in that problem that I didn't see the simplest solution ;)

The error comes about because you have not actually infered a memory for v_memory, you have infered registers - and then you get the multiple driver errors.

It is strange that you didn't get an error the first time. It could be that Quartus managed to do an optimization or synthesize your code as a memory block before it cold realize that you had two processes writing to the same signal.

I suggest to use the Quartus VHDL templates as a starting point. They include e.g. "True Dual-Port RAM with dual clock".

Oh, that's strange! I wrote an answer yesterday, but somehow it didn't appear here until now...

  SHARED VARIABLE v_memory       : ramtype;
  ATTRIBUTE ramstyle             : STRING;
  ATTRIBUTE ramstyle OF v_memory : VARIABLE IS "M10K";

The ramstyle attribute can only be used if the synthesis actually infers a ram. If you kept your previous code, you will not infer an altsyncram, just registers, hence the error.

The code needs to describe exactly what the M10K block can do, or it will be synthesized as registers. You may have something in our code that makes it behave slightly differently and Quartus can't map it to a M10K.

Hello Everybody,

  -----------------------------------------------------------------------------
  -- Dual Ported RAM Declaration + attributes
  -----------------------------------------------------------------------------
  SHARED VARIABLE ram  : ram_t := initramfromfile(g_mem_ini_file);
  SIGNAL s_data_read_a : word_t;
  SIGNAL s_data_read_b : word_t;
  ATTRIBUTE ramstyle        : STRING;
  ATTRIBUTE ramstyle OF ram : VARIABLE IS "M10K, no_rw_check";
  ATTRIBUTE ram_init_file        : STRING;
  ATTRIBUTE ram_init_file OF ram : VARIABLE IS g_mem_ini_file;
  -----------------------------------------------------------------------------
BEGIN  -- rtl
  s_int_address_a <= conv_integer(address_a);
  s_int_address_b <= conv_integer(address_b);
  -- Reorganize the read data from the RAM to match the output
  unpack : FOR i IN 0 TO 3 GENERATE
    data_read_a(8*i + 7 DOWNTO 8*i) <= s_data_read_a(i);
    data_read_b(8*i + 7 DOWNTO 8*i) <= s_data_read_b(i);
  END GENERATE unpack;
  PROCESS(clk_a)
  BEGIN
    IF(clk_a'EVENT AND clk_a = '1') THEN
      IF(enable_a = '1') THEN
        IF(write_byte_enable_a(0) = '1') THEN
          ram(s_int_address_a)(0) := data_write_a(7 DOWNTO 0);
        END IF;
        IF write_byte_enable_a(1) = '1' THEN
          ram(s_int_address_a)(1) := data_write_a(15 DOWNTO 8);
        END IF;
        IF write_byte_enable_a(2) = '1' THEN
          ram(s_int_address_a)(2) := data_write_a(24 DOWNTO 16);
        END IF;
        IF write_byte_enable_a(3) = '1' THEN
          ram(s_int_address_a)(3) := data_write_a(31 DOWNTO 25);
        END IF;
      END IF;
      s_data_read_a <= ram(s_int_address_a);
    END IF;
  END PROCESS;
  PROCESS(clk_b)
  BEGIN
    IF(clk_b'EVENT AND clk_b = '1') THEN
      IF(enable_b = '1') THEN
        IF(write_byte_enable_b(0) = '1') THEN
          ram(s_int_address_b)(0) := data_write_b(7 DOWNTO 0);
        END IF;
        IF write_byte_enable_b(1) = '1' THEN
          ram(s_int_address_b)(1) := data_write_b(15 DOWNTO 8);
        END IF;
        IF write_byte_enable_b(2) = '1' THEN
          ram(s_int_address_b)(2) := data_write_b(23 DOWNTO 16);
        END IF;
        IF write_byte_enable_b(3) = '1' THEN
          ram(s_int_address_b)(3) := data_write_b(31 DOWNTO 24);
        END IF;
      END IF;
      s_data_read_b <= ram(s_int_address_b);
    END IF;
  END PROCESS;
END altera;

  PROCESS(clk_a)
  BEGIN
    IF(clk_a'EVENT AND clk_a = '1') THEN
      IF(enable_a = '1') THEN
        FOR i IN 0 TO 3 LOOP
        IF(write_byte_enable_a(i) = '1') THEN
          ram(s_int_address_a)(i) := data_write_a(8*i+7 DOWNTO 8*i);
        END IF;          
        END LOOP;
      END IF;
      s_data_read_a <= ram(s_int_address_a);
    END IF;
  END PROCESS;

  IMPURE FUNCTION initramfromfile (ramfilename : STRING) RETURN ram_t IS
    FILE ini_file     : TEXT OPEN READ_MODE IS ramfilename;
    VARIABLE fileline : LINE;
    VARIABLE ram_dp   : ram_t := (OTHERS => (OTHERS => (OTHERS => '0')));
    VARIABLE data_slv : STD_LOGIC_VECTOR(7 DOWNTO 0);
    VARIABLE char     : CHARACTER;
  BEGIN
    FOR i IN ram_t'RANGE LOOP
      IF (NOT endfile(ini_file)) THEN  
        FOR j IN 3 DOWNTO 0 LOOP
          ram_dp(i)(j) := (OTHERS => '1');
        END LOOP;  -- j
      ELSE
        FOR j IN 3 DOWNTO 0 LOOP
          ram_dp(i)(j) := (OTHERS => '1');
        END LOOP;
      END IF;
    END LOOP;
    
    -- check if declared memory size is sufficient
    ASSERT (endfile(ini_file))
      REPORT "Memory is too small!"
      SEVERITY FAILURE;
    
    RETURN ram_dp;
  END function;

IF (NOT endfile(ini_file)) THEN 
END IF;