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Altera_Forum
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11 years ago

Problems synthesizeing infered true dual ported RAM

Hello Everybody, I'm pretty new to the Altera World and just hit some problems while trying to synthesize an infering true dual ported RAM. I already found some code snips but I didn't find the 10...
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Altera_Forum
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11 years ago

I suggest to use the Quartus VHDL templates as a starting point. They include e.g. "True Dual-Port RAM with dual clock".

It's declaring the RAM object as shared variable.