Problems synthesizeing infered true dual ported RAM

The error comes about because you have not actually infered a memory for v_memory, you have infered registers - and then you get the multiple driver errors.

You have two enables - which is not supported in syncram. You need a single write enable and single read enable.

As a side note: your code is horrible - so many type conversions. Why not stick to std_logic_vectors (instead of bitvectors mixed with std_logic_vectors) and how about some intermediate steps via variables, or maybe some more appropriate types?