Problems synthesizeing infered true dual ported RAM

Thanks for your reply PietervanderStar! You're right, combining the logic to one process solves that problem, thanks. I was probably so sucked up in that problem that I didn't see the simplest solution ;)

I used the two processes to being able to use two different clock domains for my RAM.

But what I still don't quite understand is why the first code snips worked, since I also had there two processes. From my understanding I just used a specific part of the data vector and it didn't work. But using the whole data vector is working?!