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Altera_Forum
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11 years ago

Problems synthesizeing infered true dual ported RAM

Hello Everybody, I'm pretty new to the Altera World and just hit some problems while trying to synthesize an infering true dual ported RAM. I already found some code snips but I didn't find the 10...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Oh, that's strange! I wrote an answer yesterday, but somehow it didn't appear here until now...

First of all, thanks to everybody for your help!

@Tricky: You are right! I did run through the synthesis with only one process used (like PietervanderStar suggested) and blasted the FPGA resources...

@Daixiwen: Thanks for the suggested document. Yes, I actually had a look at this document and this example. Do you know if I might hit some troubles using this together with the RAM initialisation (page 13-35, example 13-28)?

@FvM: Thanks for the suggested code. I actually started from the scratch with this code and at some point I just did something wrong so I hit this error.

I think the biggest problem is that I actually didn't get a RAM out of my design. So far I used the following attributes: 


  SHARED VARIABLE v_memory       : ramtype;
  ATTRIBUTE ramstyle             : STRING;
  ATTRIBUTE ramstyle OF v_memory : VARIABLE IS "M10K";

Since I'm using a Cyclone V, I thought Quartus would use the M10K without any troubles. But it turned out it doesn't:

can't infer memory for variable 'v_memory' with attribute '"M10K"'.

Are there any restrictions which I didn't find in the documents yet (I'm using the "Internal Memory (RAM and ROM) User Guide"?

Thanks everybody for your help! I wish you a great and sunny weekend!