Problem simulating Nios II design and external logic

Look in the vhdl file with the same name as the .sopc file you generated in SOPC builder. At the bottom of the file is places you could add your own logic to the simulation.

Indeed we find the test bench of the system at the end of the file. So I add my component with "component" and then "port map", but I have the following warning in ModelSim, and indeed, the component does not appear in the instances :

entity test_bench is 
end entity test_bench;
architecture europa of test_bench is
component processor is 
           port (
                 -- 1) global signals:
                    signal clk : IN STD_LOGIC;
                    signal reset_n : IN STD_LOGIC;
                 -- the_led_pio
                    signal out_port_from_the_led_pio : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                 -- the_test_component_conduit
                    signal coe_avs_address_from_the_test_component_conduit : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
                    signal coe_avs_chipselect_from_the_test_component_conduit : OUT STD_LOGIC;
                    signal coe_avs_read_from_the_test_component_conduit : OUT STD_LOGIC;
                    signal coe_avs_readdata_to_the_test_component_conduit : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal coe_avs_write_from_the_test_component_conduit : OUT STD_LOGIC;
                    signal coe_avs_writedata_from_the_test_component_conduit : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
                    signal coe_csi_clk_from_the_test_component_conduit : OUT STD_LOGIC;
                    signal coe_csi_reset_from_the_test_component_conduit : OUT STD_LOGIC
                 );
end component processor;
                signal clk :  STD_LOGIC;
                signal coe_avs_address_from_the_test_component_conduit :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal coe_avs_chipselect_from_the_test_component_conduit :  STD_LOGIC;
                signal coe_avs_read_from_the_test_component_conduit :  STD_LOGIC;
                signal coe_avs_readdata_to_the_test_component_conduit :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal coe_avs_write_from_the_test_component_conduit :  STD_LOGIC;
                signal coe_avs_writedata_from_the_test_component_conduit :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal coe_csi_clk_from_the_test_component_conduit :  STD_LOGIC;
                signal coe_csi_reset_from_the_test_component_conduit :  STD_LOGIC;
                signal cpu_data_master_irq :  STD_LOGIC_VECTOR (31 DOWNTO 0);
                signal out_port_from_the_led_pio :  STD_LOGIC_VECTOR (7 DOWNTO 0);
                signal reset_n :  STD_LOGIC;
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add your component and signal declaration here
component TestComponent is
    port(csi_clk : IN STD_LOGIC;
         csi_reset : IN STD_LOGIC;
         avs_chipselect : IN STD_LOGIC;
         avs_write : IN STD_LOGIC;
         avs_read : IN STD_LOGIC;
         avs_address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         avs_writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
         avs_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
    );
end component;
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
begin
  --Set us up the Dut
  DUT : processor
    port map(
      coe_avs_address_from_the_test_component_conduit => coe_avs_address_from_the_test_component_conduit,
      coe_avs_chipselect_from_the_test_component_conduit => coe_avs_chipselect_from_the_test_component_conduit,
      coe_avs_read_from_the_test_component_conduit => coe_avs_read_from_the_test_component_conduit,
      coe_avs_write_from_the_test_component_conduit => coe_avs_write_from_the_test_component_conduit,
      coe_avs_writedata_from_the_test_component_conduit => coe_avs_writedata_from_the_test_component_conduit,
      coe_csi_clk_from_the_test_component_conduit => coe_csi_clk_from_the_test_component_conduit,
      coe_csi_reset_from_the_test_component_conduit => coe_csi_reset_from_the_test_component_conduit,
      out_port_from_the_led_pio => out_port_from_the_led_pio,
      clk => clk,
      coe_avs_readdata_to_the_test_component_conduit => coe_avs_readdata_to_the_test_component_conduit,
      reset_n => reset_n
    );
  process
  begin
    clk <= '0';
    loop
       wait for 10 ns;
       clk <= not clk;
    end loop;
  end process;
  PROCESS
    BEGIN
       reset_n <= '0';
       wait for 200 ns;
       reset_n <= '1'; 
    WAIT;
  END PROCESS;
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
--add additional architecture here
CUT : TestComponent
port map(csi_clk => coe_csi_clk_from_the_test_component_conduit,
         csi_reset => coe_csi_reset_from_the_test_component_conduit,
         avs_chipselect => coe_avs_chipselect_from_the_test_component_conduit,
         avs_write => coe_avs_write_from_the_test_component_conduit,
         avs_read => coe_avs_read_from_the_test_component_conduit,
         avs_address => coe_avs_address_from_the_test_component_conduit,
         avs_writedata => coe_avs_writedata_from_the_test_component_conduit,
         avs_readdata => coe_avs_readdata_to_the_test_component_conduit);
         
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
end europa;
--synthesis translate_on

Have you added the file containing your test component to the modelsim project, and compiled it? If not that may be the problem.

Yes, that was the problem. We have to add the vhdl file to the ModelSim project and compile it before. Thanks for your help.