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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem during synthesization

I tried to synthesize my design in Quartus II version 8.0. During the synthesization, the error is:

Error (10394): VHDL error at zpu_core.vhd(874): left bound of range must be a constant

When i clicked this, the following is highlighted:

stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));

When i synthesize my design in Mentor Graphic HDL Designer, this is no problem at all. Maybe the Quartus that i'm using need to configured correctly?? Anyone has idea on this???

Thx

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Does (wordBytes-1-to_integer(stackA(byteBits-1 downto 0))) contain a VHDL signal that can be changed to a variable? Quartus integrated synthesis can calculate the range bounds from variables but not from signals.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    it doesn't contain signal that can be changed into variable.Maybe can i change some setting in my Quartus??

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You can't make Quartus accept a signal in a range bound calculation.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    So wordBytes, stackA and byteBits are all constants? My guess is some are signals, which Quartus Integrated Synthesis doesn't accept. I think(emphasize think) you could put this into a for-loop, where the integer goes from one of these values up to that plus 8.

    Another concern, if I'm reading this correctly, is that mem_read seems to be some giant vector meant to be a RAM. For example, if you wanted a 256x8 RAM, you just made a signal that is 2047 downto 0 and then access it in 8 bit chunks. If that's what your intent is, I would suggest looking in the Quartus II Handbook at HDL coding guidelines for inferring a RAM, which is normally done with an array, so that the width is much more explicit than just inices that are i to i+8. I'm just taking a guess what you're doing, so ignore if that's not relevant.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I have such a problem too.

    Were you able to solve?

    --- Quote End ---

    The problem above already has a solution.

    You will have to post up your code to see what your problem is.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    rc1_fifo_data(31 downto 0) <= rx_data((32*(conv_integer(state_counter(6 downto 1)))+31) downto (32*(conv_integer(state_counter(6 downto 1)))));

    Expression above is in the case statement.

    rc1_fifo_data is OUT std_logic_vector(32 downto 0)

    rx_data is IN std_logic_vector((rx_num*32)-1 downto 0)

    rx_num is generic integer

    state_counter is an internal signal

    when I tried to use variable instead of "conv_integer(state_counter(6 downto 1))" I got the same error message again; "left bound of the range must be a constant"

    Am I wrong?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Actually this block is connected to the user-defined number of rx.vhd block whose output is std_logic_vector(32 downto 0).

    I combined the rx.vhd blocks as rx_generic.vhd. So its output became a std_logic_vector(rx_num*32-1 downto 0). This forced me to use such a wide std_logic_vector.

    But I couldn't understand how can I use array type in such a situation.

    I can't define an IN port with array type, can I?

    Or, Should I define an internal array and put the incomming 32bit datas to it then use?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    yes you can use any type on a port declaration. The type has to be declared in a package.