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Altera_Forum's avatar
Altera_Forum
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17 years ago

Problem during synthesization

I tried to synthesize my design in Quartus II version 8.0. During the synthesization, the error is:

Error (10394): VHDL error at zpu_core.vhd(874): left bound of range must be a constant

When i clicked this, the following is highlighted:

stackA(7 downto 0) <= unsigned(mem_read(((wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-to_integer(stackA(byteBits-1 downto 0)))*8));

When i synthesize my design in Mentor Graphic HDL Designer, this is no problem at all. Maybe the Quartus that i'm using need to configured correctly?? Anyone has idea on this???

Thx

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    As you said I defined such an array type in package whose dimensions were generic integers and used this array type in port decleration. In that case, I got errors again because I was not allowed to use generics, I had to use constants instead. This makes my control on my codes very complicated

    I did the previous synthesis in Quartus 8.1 and as I said before it gave me such an error.

    I think Quartus 9.1 is able to solve this case.

    I didn't get such errors when I synthesized my code with Q9.1

    I think Altera solved this "left bound of range must be a constant" issue in Q9.1 even we defined a long std_logic_Vectors with generic intergers.