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Altera_Forum
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17 years ago

Problem during synthesization

I tried to synthesize my design in Quartus II version 8.0. During the synthesization, the error is: Error (10394): VHDL error at zpu_core.vhd(874): left bound of range must be a constant W...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Does (wordBytes-1-to_integer(stackA(byteBits-1 downto 0))) contain a VHDL signal that can be changed to a variable? Quartus integrated synthesis can calculate the range bounds from variables but not from signals.