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Altera_Forum
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17 years ago

Problem during synthesization

I tried to synthesize my design in Quartus II version 8.0. During the synthesization, the error is: Error (10394): VHDL error at zpu_core.vhd(874): left bound of range must be a constant W...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Actually this block is connected to the user-defined number of rx.vhd block whose output is std_logic_vector(32 downto 0).

I combined the rx.vhd blocks as rx_generic.vhd. So its output became a std_logic_vector(rx_num*32-1 downto 0). This forced me to use such a wide std_logic_vector.

But I couldn't understand how can I use array type in such a situation.

I can't define an IN port with array type, can I?

Or, Should I define an internal array and put the incomming 32bit datas to it then use?