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Altera_Forum
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17 years ago

Problem during synthesization

I tried to synthesize my design in Quartus II version 8.0. During the synthesization, the error is: Error (10394): VHDL error at zpu_core.vhd(874): left bound of range must be a constant W...
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Altera_Forum
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15 years ago

rc1_fifo_data(31 downto 0) <= rx_data((32*(conv_integer(state_counter(6 downto 1)))+31) downto (32*(conv_integer(state_counter(6 downto 1)))));

Expression above is in the case statement.

rc1_fifo_data is OUT std_logic_vector(32 downto 0)

rx_data is IN std_logic_vector((rx_num*32)-1 downto 0)

rx_num is generic integer

state_counter is an internal signal

when I tried to use variable instead of "conv_integer(state_counter(6 downto 1))" I got the same error message again; "left bound of the range must be a constant"

Am I wrong?