problem (?) using shared variables

Well I just tried modesim and your first code works as temp1 and temp2 increment but digit1 and digit2 stay 0

true and I get warning saying shared variables must be of type protected. God knows how to protect them.

I know - and its only for simulation. A protected type is a bit like a class in C++. They contain member variables, functions and procedures and can be extremly useful for behavioural modelling. In VHDL 2002, they made it a LRM rule that shared variables MUST be protected types, but as this would break old VHDL '93 code, and so by default it only throws a warning (you can make it stricter though).

type DDR_model_t is protected
  procedure write_data(addr : integer; data : std_logic_vector);
  impure function read_data(addr: integer) return std_logic_vector;
end proteted DDR_Model_t;
type ddr_model_t is protected body
  type mem_row_t is array(0 to 1023) of std_logic_vector(31 downto 0);
  type mem_row_ptr_t is access mem_row_t;
  
  type mem_bank_t is array(0 to 1023) of mem_row_ptr_t;
  type mem_bank_ptr_t is access mem_bank_t;
    
  type mem_t is array(0 to 7) of mem_bank_ptr_t;
  
  variable mem : mem_t;  
  
  procedure write_data(addr: integer; data : std_logic_vector) is
    variable bank, row, col : integer;
  begin  
    bank = addr rem 8;
    row  = (addr/8)/1024;
    col  = (addr rem 1024);
    
    if mem(bank) = null then
      mem(bank)           := new mem_bank_t;
    end if;
      
    if mem(bank)(row) = null then
      mem(bank)(row)      := new mem_row_t;      
    end if;
  
    mem(bank)(row)(col) := data;
  end procedure write_data;
  
  impure function read_data(addr: integer) return std_logic_vector is
    variable bank, row, col : integer;
    CONSTANT ALL_U : std_logic_vector(31 downto 0) := (others => 'U');
  begin  
     bank = addr rem 8;
    row  = (addr/8)/1024;
    col  = (addr rem 1024);
    
    if mem(bank) = null or mem(bank)(row) = null then
      return ALL_U;
    else
      return mem(bank)(row)(col);
    end if;
  end function read_data;
end protected ddr_model_t;
shared variable ddr_model : ddr_model_t;
--to use it:
ddr_model.write_data(a);
some_var := ddr_model.read_data(b);

They also can be useful for handling event queues (like a load of packets arriving on a PCIe bus) - as you can have pointers in VHDL you can make linked lists of an infinite size during simulation

Tricky,

process(clk)
begin
  if rising_edge(clk) then
    cnt <= cnt + 1;
    
    if cnt = N then -- this will give you an enable rate of clk/N
      clk_en <= '1';
    else
      clk_en <= '0';
    end if;
    if clk_en = '1' then
      --do something once every N clocks
    end if;
end process;

process(clk)
begin
  if rising_edge(clk) then
    cnt <= cnt + 1;
    
    if cnt = N then -- this will give you an enable rate of clk/N
      clk_en <= '1';
    else
      clk_en <= '0';
    end if;
    if clk_en = '1' then
      --do something once every N clocks
    end if;
end process;

library ieee;
use ieee.std_logic_1164.all;
entity clock_gen is
   generic(N: integer := 50_000_000);
   port(
      mclk:  in std_logic;
	rst:  in std_logic;
	clk: out std_logic);
end clock_gen;
architecture arch of clock_gen is
   signal    cnt: integer := 0;
   signal clk_en: integer := 0;
   signal  state: integer := 0;
begin
   process(mclk, rst)
   begin
      if(rst = '1') then
         cnt <= 0;
	 clk_en <= 0;
	 state <= 0;
      elsif(rising_edge(mclk)) then
         cnt <= cnt + 1;
	 if(cnt = N) then -- this will give you an enable rate of clk/N
            clk_en <= 1;
         else
            clk_en <= 0;
         end if;
         if(clk_en = 1) then --do something once every N clocks
            if(state = 0) then
               clk <= '1';
               state <= 1;
	   else 
	      clk <= '0';
	      state <=0;
	   end if;
         end if;
      end if;
   end process;
end arch;

you shouldnt use clk_en to generate a clock. Forget about generating a 2nd clock. Just use the clk_en directly.