problem (?) using shared variables

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Ill give you the outline - its very similar to what you're doing:

process(clk)
begin
  if rising_edge(clk) then
    cnt <= cnt + 1;
    
    if cnt = N then -- this will give you an enable rate of clk/N
      clk_en <= '1';
    else
      clk_en <= '0';
    end if;
    if clk_en = '1' then
      --do something once every N clocks
    end if;
end process;

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Forgetting momentarily the shared variables stuff and concentrating only in a simple clock generator based on this piece of code you provided, I developed the following code:

library ieee;
use ieee.std_logic_1164.all;
entity clock_gen is
   generic(N: integer := 50_000_000);
   port(
      mclk:  in std_logic;
	rst:  in std_logic;
	clk: out std_logic);
end clock_gen;
architecture arch of clock_gen is
   signal    cnt: integer := 0;
   signal clk_en: integer := 0;
   signal  state: integer := 0;
begin
   process(mclk, rst)
   begin
      if(rst = '1') then
         cnt <= 0;
	 clk_en <= 0;
	 state <= 0;
      elsif(rising_edge(mclk)) then
         cnt <= cnt + 1;
	 if(cnt = N) then -- this will give you an enable rate of clk/N
            clk_en <= 1;
         else
            clk_en <= 0;
         end if;
         if(clk_en = 1) then --do something once every N clocks
            if(state = 0) then
               clk <= '1';
               state <= 1;
	   else 
	      clk <= '0';
	      state <=0;
	   end if;
         end if;
      end if;
   end process;
end arch;

Implementing it to blink a simple led receiving clk at expected 1 Hz, this doesn´t work. The led blinks (full period) at every 174 seconds. This period stay fixed no matter N is changed.

Any idea?

Regards

Jaraqui