problem (?) using shared variables

I know - and its only for simulation. A protected type is a bit like a class in C++. They contain member variables, functions and procedures and can be extremly useful for behavioural modelling. In VHDL 2002, they made it a LRM rule that shared variables MUST be protected types, but as this would break old VHDL '93 code, and so by default it only throws a warning (you can make it stricter though).

so, as an example:

type DDR_model_t is protected
  procedure write_data(addr : integer; data : std_logic_vector);
  impure function read_data(addr: integer) return std_logic_vector;
end proteted DDR_Model_t;
type ddr_model_t is protected body
  type mem_row_t is array(0 to 1023) of std_logic_vector(31 downto 0);
  type mem_row_ptr_t is access mem_row_t;
  
  type mem_bank_t is array(0 to 1023) of mem_row_ptr_t;
  type mem_bank_ptr_t is access mem_bank_t;
    
  type mem_t is array(0 to 7) of mem_bank_ptr_t;
  
  variable mem : mem_t;  
  
  procedure write_data(addr: integer; data : std_logic_vector) is
    variable bank, row, col : integer;
  begin  
    bank = addr rem 8;
    row  = (addr/8)/1024;
    col  = (addr rem 1024);
    
    if mem(bank) = null then
      mem(bank)           := new mem_bank_t;
    end if;
      
    if mem(bank)(row) = null then
      mem(bank)(row)      := new mem_row_t;      
    end if;
  
    mem(bank)(row)(col) := data;
  end procedure write_data;
  
  impure function read_data(addr: integer) return std_logic_vector is
    variable bank, row, col : integer;
    CONSTANT ALL_U : std_logic_vector(31 downto 0) := (others => 'U');
  begin  
     bank = addr rem 8;
    row  = (addr/8)/1024;
    col  = (addr rem 1024);
    
    if mem(bank) = null or mem(bank)(row) = null then
      return ALL_U;
    else
      return mem(bank)(row)(col);
    end if;
  end function read_data;
end protected ddr_model_t;
shared variable ddr_model : ddr_model_t;
--to use it:
ddr_model.write_data(a);
some_var := ddr_model.read_data(b);

And then wrap an entity around this shared variable to make it behave like a DDR chip, but it will only use system ram as individual rows are accesses, so you dont need to use a massive amount of ram during simulation to model the memory, and it runs much faster.