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Altera_Forum
Honored Contributor
Honored Contributorproblem (?) using shared variables
Hi, I need your kind opinion. Please, anyone explain me why the following code is not running. VHDL code (sel-explainable)
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en...
Altera_ForumHonored Contributor
Honored Contributoryou shouldnt use clk_en to generate a clock. Forget about generating a 2nd clock. Just use the clk_en directly.
