Power Delivery Network (PDN) Tool

It is the total number of capacitors. With BGA you shouldn't decouple the pins individually. Connect all VCCINT pins to the power plane through individual vias, and also connect each capacitor to the plane through individual vias. The number of BGA pins and the number of capacitors aren't necessarily related.

Be sure that you configured the PDN with the correct current consumption on all rails. I usually use greater values that what I get from PowerPlay to have a safety margin.

Hi,

Thx for the reply.

On altera web page I read that there should be a decoupling cap on each vccint or vccio pin respectively. Do you have any thought on that? I am missing something?

Thanks

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On altera web page I read that there should be a decoupling cap on each vccint or vccio pin respectively. Do you have any thought on that? I am missing something?

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Once you have decided that you need to put a decoupling capacitor across a pair of BGA vias (between VCCINT or VCCIO and a ground via), then you should have the vias tented (epoxy filled prior to the last plating step for the bottom of the PCB ). If you're tenting one power via, you may as well tent all power vias (and remove the solder mask from the bottoms of the signal vias so you can probe them with an oscilloscope).

I personally recommend tenting the vias, and placing decoupling capacitors on every single power via.

If you want to see an example design that took this approach, see the documentation on this page:

http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/)

The 1.2V core supply can implement a 60A load step while maintaining core regulation within the required data sheet specification.

The schematic and PCB design files are there. Feel free to download and look at them. The boards were manufactured by DDI (http://www.ddiglobal.com) and assembled by SigmaTron (http://www.sigmatronintl.com/).

Cheers,

Dave

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I personally recommend tenting the vias, and placing decoupling capacitors on every single power via.

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Just to follow this up, if you're using devices with 1mm BGA pitch then a footprint for 0402 caps can be created with round pads with 1mm centres.

On the back of the board these mirror the BGA pads on the top of the board and allow you to connect straight to the vias from the top layer.

This _almost_ makes the cap placement easy (though it's always a bit of a jigsaw).

My assembly guy prefers these round 0402 pads to the previous 'standard' ones I was using so they have become my default 0402 footprint.

Nial

Hi everybody

well now i am getting a little bit confused here. Should i put decoupling caps on each pin/via of FPGA's power network (VCCINT, VCCIO) or not. How do i understand the number of cap suggested by PDN tool?

Thanks in advance

Hi Nial

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Just to follow this up, if you're using devices with 1mm BGA pitch then a footprint for 0402 caps can be created with round pads with 1mm centres.

On the back of the board these mirror the BGA pads on the top of the board and allow you to connect straight to the vias from the top layer.

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So your pads are placed in the PCB spaced between the vias, and you don't tent the vias? Did you have any issues with solder wicking into the vias?

I did try a small run of boards without tenting the vias. Inspection (flying probe and X-ray) showed there were a lot of poor contacts due to solder wicking into vias, resulting in a lot of manual rework.

The recommendation we received from SigmaTron was to tent the vias and place the 0402 caps (and any LVDS termination resistors) across the vias.

Cheers,

Dave

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well now i am getting a little bit confused here. Should i put decoupling caps on each pin/via of FPGA's power network (VCCINT, VCCIO) or not. How do i understand the number of cap suggested by PDN tool?

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put decoupling capacitors on every power pin.

How much money are you willing to spend, and how much risk are you willing to take if you do not put the caps on every power pin?

Talk with your PCB assembly house and PCB manufacturer and ask how they can load 0402 resistors, eg., either Nial's method where the pads are between the via holes, or the method I used, where the vias are tented.

Cheers,

Dave

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Hi Nial

So your pads are placed in the PCB spaced between the vias, and you don't tent the vias? Did you have any issues with solder wicking into the vias?

I did try a small run of boards without tenting the vias. Inspection (flying probe and X-ray) showed there were a lot of poor contacts due to solder wicking into vias, resulting in a lot of manual rework.

The recommendation we received from SigmaTron was to tent the vias and place the 0402 caps (and any LVDS termination resistors) across the vias.

Cheers,

Dave

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That was badly explained (or you're being daft!).

An 0402 footprint with 0.5mm round pads at 1mm pitch can be placed on the back of the board to mirror a pair of BGA balls on the other side.

I drop the vias centrally between the BGA pads with a short stub to the pad on the top layer. I then connect the cap straight to the via on the bottom.

You'll often get a power input and GND BGA beside each other. This allows you to have a CAP directly across their associated vias on the bottom of the board.

All my vias under the BGA are tented, it's one of the things to check on my PCB signoff checklist!

Nial

put decoupling capacitors on every power pin.

100nF caps are effectively free, and the incidental cost of placing another 20 devices per FPGA in a typical board is again almost zero.

Unless you're trying to get the costs down on a board you'll be making 10's of 1000's of you might as well follow this advice. And if you are you should have the budget to experiment.

Nial

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That was badly explained (or you're being daft!).

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Both :)

I got the impression that you were putting round pads for the caps directly on the PCB bottom in the identical location to the BGA pads on the top, i.e., the round cap pads lay between the vias.

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An 0402 footprint with 0.5mm round pads at 1mm pitch can be placed on the back of the board to mirror a pair of BGA balls on the other side.

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Its not mirroring the BGA balls, the caps go on the end of the vias.

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I drop the vias centrally between the BGA pads with a short stub to the pad on the top layer. I then connect the cap straight to the via on the bottom.

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Now you're talking some sense :)

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You'll often get a power input and GND BGA beside each other. This allows you to have a CAP directly across their associated vias on the bottom of the board.

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And when you don't, you steal the via from a GPIO pin, and make that GPIO pin unusable. Before I make pin assignments, I determine which power pins are missing ground pins next to them, so I can reserve appropriate GPIO pins.

The same goes for configuration signals that need pull-ups or pull-downs (if they do not route out of the BGA).

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All my vias under the BGA are tented, it's one of the things to check on my PCB signoff checklist!

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Excellent :)

Cheers,

Daft

... erm ... Dave