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well now i am getting a little bit confused here. Should i put decoupling caps on each pin/via of FPGA's power network (VCCINT, VCCIO) or not. How do i understand the number of cap suggested by PDN tool?
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put decoupling capacitors on every power pin. How much money are you willing to spend, and how much risk are you willing to take if you do not put the caps on every power pin?
Talk with your PCB assembly house and PCB manufacturer and ask how they can load 0402 resistors, eg., either Nial's method where the pads are between the via holes, or the method I used, where the vias are tented.
Cheers,
Dave
Honored Contributor
