Please help me with setup slack error

I understand you have three ADC clocks each at 8MHz then I will try this:

Assuming tCO = half clock period, you may lower min values to say 62.0

create_clock -name {adc1_cout} -period 125.000 [get_ports {ADC1_COUT }]

create_clock -name {adc2_cout} -period 125.000 [get_ports {ADC2_COUT }]

create_clock -name {adc3_cout} -period 125.000 [get_ports {ADC3_COUT }]

set_input_delay -max -clock [get_clocks {adc1_cout}] 62.5 [get_ports {ADC1_DA

[*]}]

set_input_delay -add_delay -min -clock [get_clocks {adc1_cout}] 62.5 [get_ports {ADC1_DA

[*]}]

set_input_delay -max -clock [get_clocks {adc2_cout}] 62.5 [get_ports {ADC2_DA

[*]}]

set_input_delay -add_delay -min -clock [get_clocks {adc2_cout}] 62.5 [get_ports {ADC2_DA

[*]}]

set_input_delay delay -max -clock [get_clocks {adc3_cout}] 62.5 [get_ports {ADC3_DA

[*]}]

set_input_delay -add_delay -min -clock [get_clocks {adc3_cout}] 62.5 [get_ports {ADC3_DA

[*]}]

Thank you very much for your reply, kaz!

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I understand you have three ADC clocks each at 8MH

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This is exactly what I meant.

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create_clock -name {adc1_cout} -period 125.000 [get_ports {ADC1_COUT }]

create_clock -name {adc2_cout} -period 125.000 [get_ports {ADC2_COUT }]

create_clock -name {adc3_cout} -period 125.000 [get_ports {ADC3_COUT }]

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I am not convinced if three ADCs' output will come out at the same time, so this may produce better timing.

Also, I went through the AN433 and found a method using virtual clock to constrain the design(I will definitely split "adc_virt_cout" into three virtual clocks later. :) ):

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set_input_delay -add_delay -max -clock [get_clocks {adc_virt_cout}] 23.250 [get_ports {ADC1_DA[0]}]

set_input_delay -add_delay -min -clock [get_clocks {adc_virt_cout}] 2.000 [get_ports {ADC1_DA[0]}]

set_input_delay -add_delay -max -clock [get_clocks {adc_virt_cout}] 23.250 [get_ports {ADC1_DA[1]}]

set_input_delay -add_delay -min -clock [get_clocks {adc_virt_cout}] 2.000 [get_ports {ADC1_DA[1]}]

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This considers the setup and hold relationships are not the same as they are with respect to the input clock. The input data is edge-aligned with respect to the virtual clock. The hold

requirement with respect to the virtual clock must decrease by the amount of the shift

(period/4 for a center-aligned DDR interface). The setup requirement with respect to

the virtual clock must increase by the amount of the shift (period/4 for a

center-aligned DDR interface). The input maximum and minimum delay values both

decrease by the amount of the shift (period/4 for a center-aligned DDR interface).

the period here is 125ns, divided by 4 is 31.25ns. ADC data output have setup timing of 8ns, so the input maximum delay is 62.5 - 31.25 - 8 = 23.25ns. I reserve the hold timing of 2ns. This produce the follwing timing report:

https://www.alteraforum.com/forum/attachment.php?attachmentid=3904

The setup slack is 8.21ns. This slack should represent the estimation of setup time generated by TimeQuest. What brings the variation between the setup slack and ADC setup time?

If your interface is DDR then you need further additions for falling edges.

see Timequest resource centre on altera.com

With regard to 8 ns setup time of ADC, I am not sure what you mean because ADC is an outputting device, only its tCO matters.

May be you mean maximum/minimum tCO or skew at ADC output, in that case it is fair enough to use that figure as range diff between max/min.

Hi, kaz:

Thank you for pointing out the problem.

According the ADC's datasheet, the maximum tCO is 9 ns with respect to ADC_CLK falling edge(ADC_CLK is the sample clock of ADC). The minimum tH(Output hold time from COUT to data invalid) is 2 ns, and the minimum tSU(Output hold time from COUT or COUT to data invalid) is 8 ns, both with respect to COUT rising edge(COUT is the latch clock for ADC's data outputs).

The datasheet recommends "Data out should be referenced to COUT", while it also says "The relationship between ADC_CLK and COUT is not fixed and depends on the power-on conditions".

From the recommendation of ADC datasheet, I think the relationship between COUT and tCO is not fixed. In other words, tCO varies in different power-on conditions. So tCO may be useless for the input delay constraints. That's why I refered to setup and hold timing of ADC output in my thread. Now I have no idea how to constrain my design. Can you give me some enlightment? Thanks in advance!

I am still not convinced by referring to tSU/tH of an outputting device. These are parameters that apply to inputting device(fpga in your case). It could be what ADC recommends for the receiving device.

A variable tCO would mean skew and that will be evident on min/max tCO or min/max recommended tSU/tH

Thank you for the reply.

I decide to use the tCO anyway. Maybe a little risky, but we will change the constraints based on practical result.

Thanks again for your help!