Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThank you very much for your reply, kaz!
--- Quote Start --- I understand you have three ADC clocks each at 8MH --- Quote End --- This is exactly what I meant. --- Quote Start --- create_clock -name {adc1_cout} -period 125.000 [get_ports {ADC1_COUT }] create_clock -name {adc2_cout} -period 125.000 [get_ports {ADC2_COUT }] create_clock -name {adc3_cout} -period 125.000 [get_ports {ADC3_COUT }] --- Quote End --- I am not convinced if three ADCs' output will come out at the same time, so this may produce better timing. Also, I went through the AN433 and found a method using virtual clock to constrain the design(I will definitely split "adc_virt_cout" into three virtual clocks later. :) ): --- Quote Start --- set_input_delay -add_delay -max -clock [get_clocks {adc_virt_cout}] 23.250 [get_ports {ADC1_DA[0]}] set_input_delay -add_delay -min -clock [get_clocks {adc_virt_cout}] 2.000 [get_ports {ADC1_DA[0]}] set_input_delay -add_delay -max -clock [get_clocks {adc_virt_cout}] 23.250 [get_ports {ADC1_DA[1]}] set_input_delay -add_delay -min -clock [get_clocks {adc_virt_cout}] 2.000 [get_ports {ADC1_DA[1]}] --- Quote End --- This considers the setup and hold relationships are not the same as they are with respect to the input clock. The input data is edge-aligned with respect to the virtual clock. The hold requirement with respect to the virtual clock must decrease by the amount of the shift (period/4 for a center-aligned DDR interface). The setup requirement with respect to the virtual clock must increase by the amount of the shift (period/4 for a center-aligned DDR interface). The input maximum and minimum delay values both decrease by the amount of the shift (period/4 for a center-aligned DDR interface). the period here is 125ns, divided by 4 is 31.25ns. ADC data output have setup timing of 8ns, so the input maximum delay is 62.5 - 31.25 - 8 = 23.25ns. I reserve the hold timing of 2ns. This produce the follwing timing report: https://www.alteraforum.com/forum/attachment.php?attachmentid=3904 The setup slack is 8.21ns. This slack should represent the estimation of setup time generated by TimeQuest. What brings the variation between the setup slack and ADC setup time?