Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Please help me with setup slack error

Hi: I use FPGA to capture 6 channel ADC output simutaneously. The pin of ADC output clock is COUT and 8MHz. The width of ADC output data is 16 bits. The time of valid data is about half of the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hi, kaz:

Thank you for pointing out the problem.

According the ADC's datasheet, the maximum tCO is 9 ns with respect to ADC_CLK falling edge(ADC_CLK is the sample clock of ADC). The minimum tH(Output hold time from COUT to data invalid) is 2 ns, and the minimum tSU(Output hold time from COUT or COUT to data invalid) is 8 ns, both with respect to COUT rising edge(COUT is the latch clock for ADC's data outputs).

The datasheet recommends "Data out should be referenced to COUT", while it also says "The relationship between ADC_CLK and COUT is not fixed and depends on the power-on conditions".

From the recommendation of ADC datasheet, I think the relationship between COUT and tCO is not fixed. In other words, tCO varies in different power-on conditions. So tCO may be useless for the input delay constraints. That's why I refered to setup and hold timing of ADC output in my thread. Now I have no idea how to constrain my design. Can you give me some enlightment? Thanks in advance!