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Altera_Forum
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14 years ago

Please help me with setup slack error

Hi: I use FPGA to capture 6 channel ADC output simutaneously. The pin of ADC output clock is COUT and 8MHz. The width of ADC output data is 16 bits. The time of valid data is about half of the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

If your interface is DDR then you need further additions for falling edges.

see Timequest resource centre on altera.com

With regard to 8 ns setup time of ADC, I am not sure what you mean because ADC is an outputting device, only its tCO matters.

May be you mean maximum/minimum tCO or skew at ADC output, in that case it is fair enough to use that figure as range diff between max/min.