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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Since the details of the impacted design are essential for a more in-depth analysis and resolution and without it, it will be difficult for us to further debug. With that, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!


Best Regards,

Richard Tan



  • FHint's avatar
    FHint
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    I'll try to remove everything from the design, that is not necessary to reproduce the problem and keep everything that can be shared by corporate regulations. Maybe it's enough to just keep the MSGDMA Intel IP core and basic qsys-hierarchy to cause the issue.

    I can not yet say when I'll be finished with the reduced design but I'd answer this thread again when it's done - if that's ok?

    Best Regards