Forum Discussion

FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I have now found a component that enormously improves the performance when removed: the Modular Scatter-Gather DMA Intel FPGA IP.
This IP core is instantiated 8 times in the whole design and I removed all the instances.
This is the difference it makes when compiling the design:

Nothing else has been changed in the design.
Opening the top level QSYS file now only takes about 15 minutes instead of at least an hour.

All the instances of the MSGDMA share their parameters.
Is there any way to instantiate the MSGDMA without the performance impact?
Is it possible to instantiate pre-compiled code in the platform designer?

Best Regards,
Florian