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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I have now also removed the elaboration callback function from the component that is instantiated ~60 times but the performance when opening the top level system hasn't improved at all.

Is there anything else I can look into? Does the platform designer generate detailed logs when opening a file? Is it possible that the platform designer times out over and over again because it can't find certain files or tries to reach a server or anything like that?

I have observed that the platform designer uses about 1.4 GB of RAM while opening the system and has a CPU usage of about 7% for the whole period that it tries to open it. Do these values sound odd/too high?

Best Regards,
Florian