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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Are each of these 60 components completely unique? Or are you saying that you created just one custom component and when it's instantiated, a parameter lets you select the FIFO type? If you're having 60 completely unique components all requiring to run elaboration callbacks then that could certainly be the cause.

FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

It's one generic component with 25 parameters, but 16 of them are derived.
One of these parameters (non-derived) chooses which of the 5 FIFO is instantiated in the VHDL.
The other parameters are either used within the VHDL code, specify port widths or both.
The 16 derived parameters are set within the elaboration callback.

So yes, it's one custom component that is instantiated ~60 times with different parameters.