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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Have you been able to resolve your issue based on sstrell's suggestion?

I apologize for my initial response; I didn't realize that my suggestion doesn't work for Quartus Standard.


Best Regards,

Richard Tan


FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I have not yet been able to resolve the problem. I am currently trying to recreate existing (sub-)systems and instantiating hw.tcl of subsystems instead of .qsys to see whether this does improve performance.