Forum Discussion
Occasional ContributorPlatform Designer BFM simulation
Hi
I have been learning FPGA development for past few months. Now I have started using platform designer. I could generate an IP, do all the connections and generate HDL in VHDL. When I tried running a BFM simulation using Questa, the files got compiled successfully without errors and warnings. But when I run the simulation on the test bench, it shows warnings that the components in top level entity are not bound. I can't proceed further and what should I do to resolve these issues.
Moreover, are their good resources, libraries or exercises about platform designer and bus functional model simulation.
Looking for a solution for these problems.
Kind Regards
Aswin
Hi @Aswinkrishnan ,
One more thing is have you follow the BFM simulation steps of avlmm_2x2_vhdl in the screenshots below?:
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
10 Replies
ShengN_alteraSuper Contributor
Hi @Aswinkrishnan ,
Document below shows the steps related to bus functional model simulation:
Click this link to download the testbench Avalon Verification IP Suite Design Files.
Design store:
Course video:
https://learning.intel.com/Developer/learn/course/97/Avalon%2520Verification%2520Suite
Below attached the tested BFM simulation file for your refence (check image):
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
AswinkrishnanThank you for providing links to the resources page. But I can't access it because it is due to system time out or privacy restrictions. I tried changing my system to Eastern Time, yet forbidden. I was told to contact the administrator.
- ShengN_altera
Hi,
Most likely you have to get an account at Intel official website https://www.intel.com/content/www/us/en/homepage.html first in order to access those links.
Thanks,
Best Regards,
Sheng
- Aswinkrishnan
I had created the account and is logged in, but the problem still persists.
- ShengN_altera
Hi,
Document below shows the steps related to bus functional model simulation:
Intel website search for - Avalon Verification IP Suite: User Guide -> 18. Avalon-ST Verilog HDL Testbench
Design store:
Intel website search for - FPGA Design Store | Intel then click in and search for
- Cyclone 10 LP - Avalon Verification IP Suite(Single Avalon-MM Master and Slave Pair)
- Cyclone 10 LP - Avalon Verification IP Suite(Two Avalon-MM Master and Slave Pair)
Course video:Intel website go to DEVELOPERS -> Learn -> Intel® Quartus® Prime Software: Foundation -> Home and search for
- Avalon Verification Suite
- Advanced System Design Using Platform Designer: Component & System Simulation
Thanks,Best Regards,
Sheng
- ShengN_altera
Hi,
Any further update or consideration on this thread?
Let me know if you have any further concern.
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
