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Aswinkrishnan's avatar
Aswinkrishnan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Platform Designer BFM simulation

Hi I have been learning FPGA development for past few months. Now I have started using platform designer. I could generate an IP, do all the connections and generate HDL in VHDL. When I tried runn...
  • ShengN_altera's avatar
    ShengN_altera
    3 years ago

    Hi @Aswinkrishnan ,

    One more thing is have you follow the BFM simulation steps of avlmm_2x2_vhdl in the screenshots below?:

    Best regards,
    Sheng

    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Aswinkrishnan's avatar
Aswinkrishnan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I had created the account and is logged in, but the problem still persists.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Hi,

    Document below shows the steps related to bus functional model simulation:

    Intel website search for - Avalon Verification IP Suite: User Guide -> 18. Avalon-ST Verilog HDL Testbench

    Design store:

    Intel website search for - FPGA Design Store | Intel then click in and search for

    1. Cyclone 10 LP - Avalon Verification IP Suite(Single Avalon-MM Master and Slave Pair)
    2. Cyclone 10 LP - Avalon Verification IP Suite(Two Avalon-MM Master and Slave Pair)


    Course video:

    Intel website go to DEVELOPERS -> Learn -> Intel® Quartus® Prime Software: Foundation -> Home and search for

    1. Avalon Verification Suite
    2. Advanced System Design Using Platform Designer: Component & System Simulation


    Thanks,

    Best Regards,

    Sheng

    • Aswinkrishnan's avatar
      Aswinkrishnan
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Thank you for that. I have been trying out that zip files and in that I was mainly understanding avlmm_2x2_vhdl. When I tried to run the simulation on the test bench in Questa, the warnings shown are

      1. component instance "dut : avlmm_avls_2x2" is not bound.

      2. component instance "tp : test program is not bound.

      There is no simulation running. Are these errors due to libraries or something else?


      For your reference, I am using Quartus prime standard 21.1 version.

      • ShengN_altera's avatar
        ShengN_altera
        Icon for Super Contributor rankSuper Contributor
        3 years ago

        Hi,

        I'm able to run the BFM simulation of avlmm_2x2_vhdl with Questa Starter Edition check image:

        The files are attached for your reference.

        Seems like your Questa needs proper license. May be you can try with modelsim and see whether the problem persists? If there is no problem with modelsim then that'll be Questa license issue. If so, you may open a new thread at Intel® FPGA Software Installation & Licensing forum.

        Best Regards,

        Sheng

        p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.