Aswinkrishnan
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Re: Avalon mm Master BFM
I will try your suggestion. Maybe single addressable 8-bit registers could be tested. Regarding the qwork example that you provided with multiple slave IP's such as on-chip RAM, when I did run the simulation, the readdatavalid is getting asserted after a clock cycle. Hence the data that is being written to RAM will be returned xxxxxxxx's when reaching the BFM master. Therefore, what component is asserting readdatavalid and how can we remove the delay between readdata signal and readdatavalid signal? The screenshot 1 below is the console window which reads the data that is being read. The screenshot 2 below is the problem that I stated above regarding readdatavalid signal. I haven't made any changes in your program except writing to ON-chip RAM instead of PIO_control.1.7KViews0likes0CommentsRe: Avalon mm Master BFM
Thank you for the reply and I will look in to those files. I have an Avalon slave device with an 8-bit data width and multiple individually addressable 8-bit data registers with adjacent addresses. So, sometimes I want to write data to a single 8-bit data register in my address space. The BFM and/or the Avalon infrastructure are generating 4 successive addresses, not the single address I expect. It is as if the BFM and Avalon infrastructure are configured to do a 32-bit write, with 4 successive bytes of data. First, is it possible to do a single 8-bit write to my slave device? Secondly, if it is possible, what parameters should I set, and to what values, to achieve this?6.9KViews0likes0CommentsRe: Avalon mm Master BFM
The code snippet in the test bench was shared with you earlier (to push a command). That was the set of statements that I use and I believe there are no other initializations elsewhere. My doubt is that, when I write c0 to a register, why does the interconnect and the slave avs address show a range of addresses such as from c0 to c4, without specifying them?6.9KViews0likes0Comments- 7KViews0likes0Comments
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