Occasional Contributor
Occasional ContributorI will try your suggestion. Maybe single addressable 8-bit registers could be tested.
Regarding the qwork example that you provided with multiple slave IP's such as on-chip RAM, when I did run the simulation, the readdatavalid is getting asserted after a clock cycle. Hence the data that is being written to RAM will be returned xxxxxxxx's when reaching the BFM master.
Therefore, what component is asserting readdatavalid and how can we remove the delay between readdata signal and readdatavalid signal?
The screenshot 1 below is the console window which reads the data that is being read.
The screenshot 2 below is the problem that I stated above regarding readdatavalid signal.
I haven't made any changes in your program except writing to ON-chip RAM instead of PIO_control.
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