Forum Discussion
Occasional ContributorPlatform Designer BFM simulation
Hi @Aswinkrishnan ,
One more thing is have you follow the BFM simulation steps of avlmm_2x2_vhdl in the screenshots below?:
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Occasional ContributorI had created the account and is logged in, but the problem still persists.
Super ContributorHi,
Document below shows the steps related to bus functional model simulation:
Intel website search for - Avalon Verification IP Suite: User Guide -> 18. Avalon-ST Verilog HDL Testbench
Design store:
Intel website search for - FPGA Design Store | Intel then click in and search for
- Cyclone 10 LP - Avalon Verification IP Suite(Single Avalon-MM Master and Slave Pair)
- Cyclone 10 LP - Avalon Verification IP Suite(Two Avalon-MM Master and Slave Pair)
Course video:
Intel website go to DEVELOPERS -> Learn -> Intel® Quartus® Prime Software: Foundation -> Home and search for
- Avalon Verification Suite
- Advanced System Design Using Platform Designer: Component & System Simulation
Thanks,
Best Regards,
Sheng
- Aswinkrishnan
Thank you for that. I have been trying out that zip files and in that I was mainly understanding avlmm_2x2_vhdl. When I tried to run the simulation on the test bench in Questa, the warnings shown are
1. component instance "dut : avlmm_avls_2x2" is not bound.
2. component instance "tp : test program is not bound.
There is no simulation running. Are these errors due to libraries or something else?
For your reference, I am using Quartus prime standard 21.1 version.- ShengN_altera
Hi,
I'm able to run the BFM simulation of avlmm_2x2_vhdl with Questa Starter Edition check image:
The files are attached for your reference.
Seems like your Questa needs proper license. May be you can try with modelsim and see whether the problem persists? If there is no problem with modelsim then that'll be Questa license issue. If so, you may open a new thread at Intel® FPGA Software Installation & Licensing forum.
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
- ShengN_altera
Hi @Aswinkrishnan ,
One more thing is have you follow the BFM simulation steps of avlmm_2x2_vhdl in the screenshots below?:
Best regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.- Aswinkrishnan
Hi
Thanking you for all the answers now. The program seems to be working perfectly.
I was going through the test program to understand the format and the commands that are being used to communicate with the bus. The questions I have are
1. Are those commands in the test program global? that is it could be used for writing any other simulation models?
2. Are there any pdf or resources that lists all the commands, writing a bus functional model test bench?
To understand the concept of BFM in whole, I was looking for simulating a counter module. I could use it as the slave device and control it using the master. Hence, does the test program can be used as a reference for any further examples.
Regards
Aswin
