New ContributorI was trying to compile the DE5A_NET.qpf file of the `DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/PCIe_DDR4/` in Quartus Prime Pro version21.4, getting some compilation error and the error message is attached with this.
I am compiling this sample project for an Arria 10 GX FPGA with 10AX115N2F45E1SG Board.
PS: Opening the project, I got a message for IP up-gradation and I did that.
Regular ContributorHi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with the findings.
Thank you for your patience.
Best regards,
Wincent_Intel
Regular ContributorHi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
Best regards,
Wincent_Intel
Regular ContributorHi Travisa,
Can you press the small arrow on left side of Quartus Prime fitter was unsuccessful, 2 errors, 3 warning ?
It is good if we have the information on the error code to further narrow down the issue.
If I understand correctly, you are compiling the project from the provided example in the Quartus without modifying anything am I right?
Looking forward to hear back from you.
Regards,
Wincent_Intel
New ContributorHi,
For the sake of clarity I would like to explain the process from starting. Yup I did not change anything from the factory default files of DE5a-Net-DDR4_v.1.0.9_SystemCD. Also just to be clear, I am using Arria 10 GX FPGA with 10AX115N2F45E1SG Board and Quartus Prime Pro 21.4.
1) When I open the file DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/PCIe_DDR4/DE5A_NET.qpf in quartus Prime (the screen shot is attached with name `Capture.PNG`) the dialogue box for IP up gradation pops up.
2) Launching the IP upgrade tool leads to the `ep_33x8 avmm256 integrated.qsys` file upgadation windows. But I cannot select the auto-upgrade option in the tab (Shown in `Capture1.PNG`). So went for update from editor. Looks that worked.
3)But could not run generate test bench ( the screenshots are added as `Capture2.PNG` and `Capture3.PNG`).
4)Generate HDL is also gives a lot of warnings `(Capture4.PNG` and `Capture5.PNG`)
5) Went back to the project and Error on compilation of the project is captured as `Capture6.PNG`
6)I cannot generate the example design for `Intel Arria 10/Cyclone 10 Hard IP for PCI Express`. as seen in the right tab of attachment `Capture7.PNG`
7) As the first compilation error says "verilog HDL error at verilog HDL error at DESA_NET. V (389) : constant is not allowed here . The screenshot `Capture8.PNG` is with opened file DESA_NET. V and shows line 389.
I am not sure why the generate test bench and HDL are throwing errors. It would be great if someone could help?.
Thank you!
Regular ContributorHi Travis,
Thanks for such a detailed reply and the printscreen picture.
If refer to Capture 2 for error "Error: Unexpected error writing the ensemble: java.io.FileNotFoundException:"
Can you please check if The software was installed under Program Files folder ?
Let me know if the problem solved.
Regards,
Wincent_Intel
New ContributorOur installation of Quartus Prime Pro 21.4 is not under the "Program Files" Directory. It is located with a file path: C:/intelFPGA_pro folder.
Copying example projects out onto our Desktop allows for two different .qpf files to compile successfully after minor updates to our current version (specifically the Quartus Design Files of "DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstration/Hello" and "DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/NIOS_DDR4_X2"). The testbech and DHL generating are done for both examples (using their associated .qsys files) without having any error .
However, our project ("DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/PCIe_DDR4/") containing ep_g3x8_avmm256_integrated.qsys continues to get held up at the "Generate Testbench" Step in Platform Designer after the automatic updates. (Screenshot 67, Screenshot 68)
Screenshot 66 just indicates that our project doesn't compile by default.
We are thinking about Installing an older version of Quartus Prime Pro such as 18.1. As well as possibly uninstalling completely and then creating an Altera folder and installing Quartus Prime Pro there.
We already have enabled the write and read permissions of the C:/intelFPGA_pro/21.4/ip/altera folder as a whole for all users.
Thank you for your suggestions on helping us to run the PCIe DMA transfer sample project.
Regular ContributorHi,
Is it the issue still replicate in Quartus v18.1 ? if yes, maybe you can share with me the .qar file so that I can look it further.
Meanwhile, please try to clean up your project before make the generation again? This is fall under Project -> clean project.
Hoping to hear back from you.
Regards,
Wincent_Intel
New ContributorHello,
We retrograded our version of Quartus Prime Pro to 18.1. We also redownloaded the System CD provided by Terasic.
/*link may require a Terasic account*/
http://download.terasic.com/downloads/cd-rom/de5a-net-ddr4/
We opened up the ../Demonstrations/PCIe_DDR4/DE5A_NET.qpf in Quartus Prime Pro 18.1.0.222. From there we opened up ep_g3x8_avmm256_integrated.qsys in Platform Designer as part of the Auto Upgrade Process. I've attached the PCIe_DDR4.7z for our exact project after upgrades.
Generating TestBench worked fine with few warnings (see Warnings image). Generating HDL worked fine too, again with a couple warnings (see two attached images).
However Compilation of the project quickly encounters errors (see the 2 Error images).
We seem to be narrowing down the issue. We had received this exact same Compilation error in Quartus Prime Pro 21.1. Forgive me for not understanding Verilog as well as I should. But I am still working to resolve "Verilog HDL error at DE5A_NET.v(389): constant is not allowed", successfully compile our project, and program our Arria 10 GX 10AX115N2F45E1SG.
Regular ContributorHi Travis,
I think you can safely ignore the warning.
For the Verilog error, it normally happens as in a Verilog Design File (.v) at the specified location, you specified a value for a module parameter that is not a constant expression; however, parameter values must be constant expressions. My suggestion is try to edit the design so the values you assign to parameters are constant expressions.
Besides that, do you try it on a different device or Quartus version (as you mention previously in v18.0 )
Is the same error still happening?
Regards,
Wincent_Intel
Regular ContributorHi,
I wish to follow up with you about this IPS case.
Hoping to hear back from you so that we can proceed for next step.
Regards,
Wincent_Intel
New ContributorHi,
Yes we tried compilation of the project (after IP up-gradation) with Quartus Prime Pro v18.0 as well as 21.4, and unfortunately getting same error. Also when I tried to compile the /Demonstrations/PCIe_Fundamental/DE5A_NET.qpf, gets same error (screenshot attached) as gotten while compiling /Demonstrations/PCIe_DDR4/DE5A_NET.qpf.
As I am beginner in Verilog also, could you please suggest the change I have to do in bit more detail. Thank you.
Regular ContributorHi Travis,
Can you help to open this and let me see the detail error code ?
What is the 3 errors that you obtain ? beside the verilog hdl error.
Regards,
Wincent_Intel
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