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travisa's avatar
travisa
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3 years ago

PCIe DMA transfer design code Compilation error.

I was trying to compile the DE5A_NET.qpf file of the `DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/PCIe_DDR4/` in Quartus Prime Pro version21.4, getting some compilation error and the error message...
travisa's avatar
travisa
Icon for New Contributor rankNew Contributor
3 years ago

Hello,

We retrograded our version of Quartus Prime Pro to 18.1. We also redownloaded the System CD provided by Terasic.

/*link may require a Terasic account*/

http://download.terasic.com/downloads/cd-rom/de5a-net-ddr4/

We opened up the ../Demonstrations/PCIe_DDR4/DE5A_NET.qpf in Quartus Prime Pro 18.1.0.222. From there we opened up ep_g3x8_avmm256_integrated.qsys in Platform Designer as part of the Auto Upgrade Process. I've attached the PCIe_DDR4.7z for our exact project after upgrades.

Generating TestBench worked fine with few warnings (see Warnings image). Generating HDL worked fine too, again with a couple warnings (see two attached images).

However Compilation of the project quickly encounters errors (see the 2 Error images).

We seem to be narrowing down the issue. We had received this exact same Compilation error in Quartus Prime Pro 21.1. Forgive me for not understanding Verilog as well as I should. But I am still working to resolve "Verilog HDL error at DE5A_NET.v(389): constant is not allowed", successfully compile our project, and program our Arria 10 GX 10AX115N2F45E1SG.