New Contributor
Regular ContributorHi Travisa,
Can you press the small arrow on left side of Quartus Prime fitter was unsuccessful, 2 errors, 3 warning ?
It is good if we have the information on the error code to further narrow down the issue.
If I understand correctly, you are compiling the project from the provided example in the Quartus without modifying anything am I right?
Looking forward to hear back from you.
Regards,
Wincent_Intel
New ContributorHi,
For the sake of clarity I would like to explain the process from starting. Yup I did not change anything from the factory default files of DE5a-Net-DDR4_v.1.0.9_SystemCD. Also just to be clear, I am using Arria 10 GX FPGA with 10AX115N2F45E1SG Board and Quartus Prime Pro 21.4.
1) When I open the file DE5a-Net-DDR4_v.1.0.9_SystemCD/Demonstrations/PCIe_DDR4/DE5A_NET.qpf in quartus Prime (the screen shot is attached with name `Capture.PNG`) the dialogue box for IP up gradation pops up.
2) Launching the IP upgrade tool leads to the `ep_33x8 avmm256 integrated.qsys` file upgadation windows. But I cannot select the auto-upgrade option in the tab (Shown in `Capture1.PNG`). So went for update from editor. Looks that worked.
3)But could not run generate test bench ( the screenshots are added as `Capture2.PNG` and `Capture3.PNG`).
4)Generate HDL is also gives a lot of warnings `(Capture4.PNG` and `Capture5.PNG`)
5) Went back to the project and Error on compilation of the project is captured as `Capture6.PNG`
6)I cannot generate the example design for `Intel Arria 10/Cyclone 10 Hard IP for PCI Express`. as seen in the right tab of attachment `Capture7.PNG`
7) As the first compilation error says "verilog HDL error at verilog HDL error at DESA_NET. V (389) : constant is not allowed here . The screenshot `Capture8.PNG` is with opened file DESA_NET. V and shows line 389.
I am not sure why the generate test bench and HDL are throwing errors. It would be great if someone could help?.
Thank you!
