Parameter type not supported?

Hello,

When trying to use SystemVerilog parameter type to create a 'generic' fifo I get the following error

Error (10170): Verilog HDL syntax error at generic_fifo.sv(5) near text: "type"; expecting an identifier ("type" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Is parameter type not supported?

My source code below (I double checked my files support other SV constructs), Im using quartus prime standard 17.1

module generic_fifo 
# (
   parameter type T =  logic , //It seems this is not supported
   parameter DEPTH  = 2,
   parameter COUNT_SIZE = (DEPTH == 0) ? 1 : $clog2(DEPTH) 
)
(
   input  logic aclk,
   input  logic resetn,
   input  T data_in,
   input  logic push,
   input  logic pop,
   output logic  ptr,
   output logic empty,
   output logic full,
   output T data_out
);
T mem;

Cheers,

-rgarcia071