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Altera_Forum
Honored Contributor
Honored ContributorParameter type not supported?
Hello, When trying to use SystemVerilog parameter type to create a 'generic' fifo I get the following error Error (10170): Verilog HDL syntax error at generic_fifo.sv(5) near text: "ty...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It is very unlikely that a type parameter would be supported. This would open it to all sorts of potential types, that you can generally work around with a LENGTH parameter. The same is true for generic types in VHDL --- Quote End --- There is nothing un-synthesizable about a type parameter. It is just a symbolic way of representing a data type. You just need to restrict yourself to the set of synthesizable data types like you would for any variable declaration. It just a feature this tool has not gotten around to implementing it yet.
