Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorParameter type not supported?
Hello, When trying to use SystemVerilog parameter type to create a 'generic' fifo I get the following error Error (10170): Verilog HDL syntax error at generic_fifo.sv(5) near text: "ty...
Altera_ForumHonored Contributor
Honored ContributorDid you set the compiler to compile SystemVerilog or Verilog-2001 in the settings?
