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Altera_Forum
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8 years ago

Parameter type not supported?

Hello, When trying to use SystemVerilog parameter type to create a 'generic' fifo I get the following error Error (10170): Verilog HDL syntax error at generic_fifo.sv(5) near text: "ty...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Did you set the compiler to compile SystemVerilog or Verilog-2001 in the settings?

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It is set to SystemVerilog in fact I can use statements such as always_ff, and keywords like 'logic' which makes me think that parameter type T = int, and others is not supported