Need some help of SRunner Tools! Need some related files!

What do you mean by editing .rpd files? The file format is proprietary to Altera, so you do not get to edit anything. You can use Quartus to generate .rpd files, and you can use SRunner to download them.

The S in SRunner stands for Serial, since the EPCS and EPCQ are really just re-branded SPI flash devices. You can read any number of SPI flash data sheets to understand the op-code and addressing schemes used by these dvices, eg., Micron data sheets are good.

What you do not get to "learn" is what is the format of the .rpd file, eg., how do the bits in the file correspond to programming cells in the FPGA. That is the information Altera does not release.

Note: because you mentioned .rpd files, you implied you are interested in using an SPI flash for FPGA configuration. If the SPI flash is larger than the configuration file size (compressed or not), you can use the remaining flash, eg., to store NIOS processor code, or user-defined data. After the FPGA configures from the SPI flash, the SPI interface pins can be configured as user I/O and you can use an SPI master in the FPGA fabric to access the flash.

Cheers,

Dave

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What do you mean by editing .rpd files? The file format is proprietary to Altera, so you do not get to edit anything. You can use Quartus to generate .rpd files, and you can use SRunner to download them.

The S in SRunner stands for Serial, since the EPCS and EPCQ are really just re-branded SPI flash devices. You can read any number of SPI flash data sheets to understand the op-code and addressing schemes used by these dvices, eg., Micron data sheets are good.

What you do not get to "learn" is what is the format of the .rpd file, eg., how do the bits in the file correspond to programming cells in the FPGA. That is the information Altera does not release.

Note: because you mentioned .rpd files, you implied you are interested in using an SPI flash for FPGA configuration. If the SPI flash is larger than the configuration file size (compressed or not), you can use the remaining flash, eg., to store NIOS processor code, or user-defined data. After the FPGA configures from the SPI flash, the SPI interface pins can be configured as user I/O and you can use an SPI master in the FPGA fabric to access the flash.

Cheers,

Dave

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Thank you very much for replying!

Actually I'm doing some research for FPGA chip testing. I need to download the configuration file into the chip and get the inputs of the chip fixed on some specific values.(eg: there are five inputs of a circuit and these inputs are fixed on '10010') So I'm considering to edit the configuration files but I don't know whether I can achieve my purpose using tools provided by Altera. Is there any tool can be helpful?

Thanks again!

Thank you very much for replying!

Actually I'm doing some research for FPGA chip testing. I need to download the configuration file into the chip and get the inputs of the chip fixed on some specific values.(eg: there are five inputs of a circuit and these inputs are fixed on '10010') So I'm considering to edit the configuration files but I don't know whether I can achieve my purpose using tools provided by Altera. Is there any tool can be helpful?

Also, you mentioned the format is proprietary. Can I find it out by searching the patents?

Thanks again!

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Actually I'm doing some research for FPGA chip testing. I need to download the configuration file into the chip and get the inputs of the chip fixed on some specific values.(eg: there are five inputs of a circuit and these inputs are fixed on '10010') So I'm considering to edit the configuration files but I don't know whether I can achieve my purpose using tools provided by Altera. Is there any tool can be helpful?

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You should be able to use JTAG commands, along with a BSDL file to set bits in I/O cells. File a Service Request with Altera and ask them specifically how you can use JTAG to control the FPGA I/O pins using BIST (built in self test) commands.

I've never used this feature before, but others on the list may have.

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Also, you mentioned the format is proprietary. Can I find it out by searching the patents?

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Maybe. But its not really worth your time, given that the documented JTAG BIST commands and published BSDL files contain the information you need for these specific tests.

Cheers,

Dave

Thank you for giving me such suggestions!

During the last week I've been emailing with an application engineer through a Service Request. But the efficiency was really low and I got noting useful. It seems that the engineer knows nothing about it but fudged my problem.

What kind of tool should I use, if I may ask so, to execute the BIST command? Is it integrated in the Quartus Software or not? Or could you please recommend me some people or some people in the forum more reliable than the SR engineer?

Really appreciate for your help!

Best wishes,

Miao

Hi Miao,

Lets go back to your original reason for asking about JTAG and BIST;

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Actually I'm doing some research for FPGA chip testing. I need to download the configuration file into the chip and get the inputs of the chip fixed on some specific values.(eg: there are five inputs of a circuit and these inputs are fixed on '10010') So I'm considering to edit the configuration files but I don't know whether I can achieve my purpose using tools provided by Altera. Is there any tool can be helpful?

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Why can't you simply drive the inputs to 10010? You can do this with an FPGA and a cable, eg., take 5 output pins, connect them to 5 input pins, and then drive the outputs. The code to control the outputs is simple to create using Qsys.

Cheers,

Dave

Hi Dave,

I know what you mean. I've considered this but I don't want to store the input data inside the FPGA chips.

In fact, I need to set the input pins fixed to a series of data, and the size of the input data can sometimes be as large as 1MB, larger than the RAM of some FPGA chips. I've already tried to store these data in an external flash. However the flash will take too many pins from FPGA. That's why I firstly mentioned to edit the .rpd files because I was considering utilizing the EPCS chips which would take less pins.

Later, you mentioned JTAG and BIST. This may be a feasible solution because I can store the data in my computer and take no extra pins from the FGPA. As you can see, the original problem is to find a place to store the data and take as little resource(pins & RAM) as possible from the FPGA. That's why my question seems a little convoluted.

Best Wishes,

Miao

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I know what you mean. I've considered this but I don't want to store the input data inside the FPGA chips.

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Before you make that decision "final" lets discuss some of your options.

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In fact, I need to set the input pins fixed to a series of data, and the size of the input data can sometimes be as large as 1MB, larger than the RAM of some FPGA chips.

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But tiny in comparison to the SDRAM or DDR memory on many kits. For example, the DE0-nano has 32 MB SDRAM.

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I've already tried to store these data in an external flash. However the flash will take too many pins from FPGA.

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Why do you have to test all pins? The sequence you wanted above consisted of only 5 bits :)

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That's why I firstly mentioned to edit the .rpd files because I was considering utilizing the EPCS chips which would take less pins.

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You can store data in the EPCS devices without having to edit the .rpd file. The .rpd file is just the part of the EPCS device that is used for the configuration data. After the FPGA has configured, you can access any remaining areas of the Flash. In fact, you could just use a separate SPI Flash device for your needs.

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Later, you mentioned JTAG and BIST. This may be a feasible solution because I can store the data in my computer and take no extra pins from the FGPA. As you can see, the original problem is to find a place to store the data and take as little resource(pins & RAM) as possible from the FPGA. That's why my question seems a little convoluted.

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You can still store your data on your PC if you want. You can send data from your PC to the FPGA at about 600kB/s using JTAG, so 1MB of data would not take long.

Do you have an Altera development kit? Perhaps I can send you an example to run and it will help make it easier to understand your options.

Cheers,

Dave

Thanks for your patience with my problem!

Right now I have a DE2-70 kit in my hand.

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But tiny in comparison to the SDRAM or DDR memory on many kits. For example, the DE0-nano has 32 MB SDRAM.

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I have known about this and I've developed a build using the 8MB flash on the DE2 kit. I must use flash because I don't want to lose the data when the FPGA chip is power down.

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Why do you have to test all pins? The sequence you wanted above consisted of only 5 bits :)

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It's just an example of what I want to do, which might be a little misleading. Anyway, I may have to set as many as 400+ pins.:cry:

Your suggestion of using a SPI flash seems feasible. But I don't know where is the serial interface of the FPGA chip and how to use the EPCS chip as a SPI flash. Would you mind pointing me out how to deal with this problem?

If I can load the data every time I start up the FPGA from the flash on the board, without having the JTAG circuit connected, that will be my best choice! Or maybe I have to use the JTAG and BIST commands.

One more thing, I said my data could be as large as 1MB. However, the size of the data depends the circuit I test. For most circuit, the data is no more than 200KB. So we can assume the maximum size of the data is 256KB.

Best Wishes,

Miao