Honored Contributor
Honored ContributorThanks for your patience with my problem!
Right now I have a DE2-70 kit in my hand. --- Quote Start --- But tiny in comparison to the SDRAM or DDR memory on many kits. For example, the DE0-nano has 32 MB SDRAM. --- Quote End --- I have known about this and I've developed a build using the 8MB flash on the DE2 kit. I must use flash because I don't want to lose the data when the FPGA chip is power down. --- Quote Start --- Why do you have to test all pins? The sequence you wanted above consisted of only 5 bits :) --- Quote End --- It's just an example of what I want to do, which might be a little misleading. Anyway, I may have to set as many as 400+ pins.:cry: Your suggestion of using a SPI flash seems feasible. But I don't know where is the serial interface of the FPGA chip and how to use the EPCS chip as a SPI flash. Would you mind pointing me out how to deal with this problem? If I can load the data every time I start up the FPGA from the flash on the board, without having the JTAG circuit connected, that will be my best choice! Or maybe I have to use the JTAG and BIST commands. One more thing, I said my data could be as large as 1MB. However, the size of the data depends the circuit I test. For most circuit, the data is no more than 200KB. So we can assume the maximum size of the data is 256KB. Best Wishes, Miao
