Need help with testbench driving serial data out @ different clock rates, Please :)

TestBench fills an 8 bit by 16 registers array with random numbers then serially shifts it to the TDM serial input. The TDM will be coming from a Sharc DSP @ 8bit x 16 slots and continuous frames and the VHDL will demux it to various ICs. The TestBench also generates clock and frame sync for the TDM input. The 192 & 48 clocks are divided and generated internally by the VHDL code under test. Sending serial data to the TDM input works exactly as I want but I can't figure out how to send the other serial data at different clocks at the same time.

serial data to mpx_sdi @ 2 x TDM clock

serial data to aud_sdi, tnr1_sdi, tnr2_sdi @ 8 x TDM clock

I posted the TestBench code and a diagram, may be it helps.

Also I have neatly separated and colored the waveforms in modelsim for this TestBench, is there a way to save these settings so each time I need to view this particular project, I don't have to set everything each time? Cheers for all, happy Christmas and new year everyone.

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.math_real.all;

entity tdm_tb is

end tdm_tb;

architecture arch_tb of tdm_tb is

constant max_frames : natural := 5;

constant max_slot : natural := 15;

constant max_bits : natural := 7;

type my_data is array (0 to max_slot) of std_logic_vector(max_bits downto 0);

signal my_data_bit : my_data;

signal clk: std_logic;

signal rst: boolean;

signal tdm_sdi, tdm_fsi, tdm_sclki : std_logic;

signal tdm_sdo : std_logic;

signal mpx_sdi : std_logic;

signal mpx_sdo, mpx_sclk, mpx_wco : std_logic;

signal aud_sdi : std_logic;

signal aud_sdo, aud_wco, aud_sclko : std_logic;

signal hdn_sdo, hdn_wco, hdn_sclko : std_logic;

signal tnr1_sdi : std_logic;

signal tnr1_sdo, tnr1_wco, tnr1_sclko : std_logic;

signal tnr2_sdi : std_logic;

signal tnr2_sdo, tnr2_wco, tnr2_sclko : std_logic;

signal rand_num : natural := 0;

constant t_clk : time := 2 ps;

constant t_tdm : time := 3072 ps;

begin

tdm_uut: entity work.zalzett

port map (clk => clk, rst => rst,

tdm_sdi => tdm_sdi, tdm_fsi => tdm_fsi, tdm_sclki => tdm_sclki, tdm_sdo => tdm_sdo,

mpx_sdi => mpx_sdi, mpx_sdo => mpx_sdo, mpx_sclk => mpx_sclk, mpx_wco => mpx_wco,

aud_sdi => aud_sdi, aud_sdo => aud_sdo, aud_wco => aud_wco, aud_sclko => aud_sclko,

hdn_sdo => hdn_sdo, hdn_wco => hdn_wco, hdn_sclko => hdn_sclko,

tnr1_sdo => tnr1_sdo, tnr1_sdi => tnr1_sdi, tnr1_wco => tnr1_wco, tnr1_sclko => tnr1_sclko,

tnr2_sdo => tnr2_sdo, tnr2_sdi => tnr2_sdi, tnr2_wco => tnr2_wco, tnr2_sclko => tnr2_sclko);

clk <= '1' after t_clk/2 when clk = '0' else '0' after t_clk/2; --main clock

tdm_sclki <= not tdm_sclki after t_tdm/2 when rst = FALSE else '0'; -- TDM clock

--------------------random number generator

process

variable seed1, seed2: positive; -- seed values for random generator

variable rand: real; -- random real-number value in range 0 to 1.0

variable range_of_rand : real := 250.0; -- the range of random values created will be 0 to +250.

begin

for i in 0 to max_slot loop

uniform(seed1, seed2, rand); -- generate random number

rand_num <= integer(rand*range_of_rand); -- rescale to 0.250, convert integer part

my_data_bit(i) <= std_logic_vector(to_unsigned(rand_num, max_bits+1));

wait for t_tdm * (max_bits+1); --if I don't do this 'wait', numbers change without control.

end loop;

end process;

--main process

process

variable frame_cnt : natural range 0 to max_frames := 0;

variable slot_cnt : natural range 0 to max_slot := 0;

variable bit_cnt : natural range 0 to max_bits := max_bits;

begin

-----resetting the system

rst <= TRUE; tdm_fsi <= '0'; tdm_sdi <= '0'; wait for 5 ps;

rst <= FALSE;

-----new tdm frame sync

wait until rising_edge(tdm_sclki); tdm_fsi <= '1';

wait until rising_edge(tdm_sclki);

tdm_fsi <= '0';

for i in 0 to max_frames loop --frame loop

for j in 0 to max_slot loop --slot loop

for k in max_bits downto 0 loop --bit loop

tdm_sdi <= my_data_bit(j)(k);

wait until rising_edge(tdm_sclki);

if bit_cnt = 0 then

bit_cnt := max_bits;

tdm_fsi <= '0';

else

bit_cnt := bit_cnt -1;

if slot_cnt = (max_slot) and bit_cnt = 0 then

tdm_fsi <= '1';

end if;

end if;

end loop;

if slot_cnt = (max_slot) then

slot_cnt := 0;

else

slot_cnt := slot_cnt +1;

end if;

end loop;

frame_cnt := frame_cnt +1;

end loop;

wait until rising_edge(tdm_sclki);

wait until rising_edge(tdm_sclki);

wait until rising_edge(tdm_sclki);

wait until rising_edge(tdm_sclki);

end process;

end arch_tb;