Need help with testbench driving serial data out @ different clock rates, Please :)

You can run the simulation for as long as you want typing:

run X ns/us/ms/s

or even

run -all

(runs until all transactions are complete or simulation is forced to stop)

Into the console.eg:

run 100 us

runs for 100 micro seconds.

as for an example - how about this?:

data_48khz_proc : process
    variable seed1, seed2 : positive;
    variable rand         : real;
    alias internal_48khz  : std_logic is <<signal tdm_uut.some_ent1.some_ent2.clk_192khz : std_logic >>;
    
    variable rnd_val      : std_logic_vector(7 downto 0);
    
begin
    
    for bitcnt in 0 to 7 begin
        if bitcnt = 0 then
            uniform(seed1, seed2, rand); -- generate random number
            rand_num <= integer(rand*range_of_rand); -- rescale to 0.250, convert integer part 
            rnd_val <= std_logic_vector(to_unsigned(rand_num, max_bits+1));            
        end if;
        
        input <= rnd_val(bit_cnt);
        wait until rising_edge(internal_48khz);
        
    end loop;
end process;